Exception Causes (EXCCAUSE)

EXCCAU SE Code Cause Name Cause Description Required Option EXCVAD DR Loaded
0 IllegalIns tructionCa use Illegal instruction Exception No
1 SyscallCau se SYSCALL instruction Exception No
2 Instructio nFetchErro rCause Processor internal physical address or data error during instruction fetch Exception Yes
3 LoadStoreE rrorCause Processor internal physical address or data error during load or store Exception Yes
4 Level1Inte rruptCause Level-1 interrupt as indicated by set level-1 bits in the INTERRUPT register Interrupt No
5 AllocaCaus e MOVSP instruction, if caller’s registers are not in the register file Windowed Register No
6 IntegerDiv ideByZeroC ause QUOS, QUOU, REMS, or REMU divisor operand is zero 32-bit Integer Divide No
7 Reserved for Tensilica      
8 Privileged Cause Attempt to execute a privileged operation when CRING != 0 MMU No
9 LoadStoreA lignmentCa use Load or store to an unaligned address Unaligned Exception Yes
10..11 Reserved for Tensilica      
12 InstrPIFDa taErrorCau se PIF data error during instruction fetch Processor Interface Yes
13 LoadStoreP IFDataErro rCause Synchronous PIF data error during LoadStore access Processor Interface Yes
14 InstrPIFAd drErrorCau se PIF address error during instruction fetch Processor Interface Yes
15 LoadStoreP IFAddrErro rCause Synchronous PIF address error during LoadStore access Processor Interface Yes
16 InstTLBMis sCause Error during Instruction TLB refill MMU Yes
17 InstTLBMul tiHitCause Multiple instruction TLB entries matched MMU Yes
18 InstFetchP rivilegeCa use An instruction fetch referenced a virtual address at a ring level less than CRING MMU Yes
19 Reserved for Tensilica      
20 InstFetchP rohibitedC ause An instruction fetch referenced a page mapped with an attribute that does not permit instruction fetch Region Protectio n or MMU Yes
21..23 Reserved for Tensilica      
24 LoadStoreT LBMissCaus e Error during TLB refill for a load or store MMU Yes
25 LoadStoreT LBMultiHit Cause Multiple TLB entries matched for a load or store MMU Yes
26 LoadStoreP rivilegeCa use A load or store referenced a virtual address at a ring level less than CRING MMU Yes
27 Reserved for Tensilica      
28 LoadProhib itedCause A load referenced a page mapped with an attribute that does not permit loads Region Protectio n or MMU Yes
29 StoreProhi bitedCause A store referenced a page mapped with an attribute that does not permit stores Region Protectio n or MMU Yes
30..31 Reserved for Tensilica      
32..39 Coprocesso rnDisabled Coprocessor n instruction when cpn disabled. n varies 0..7 as the cause varies 32..39 Coprocess or No
40..63 Reserved      

Infos from Xtensa Instruction Set Architecture (ISA) Reference Manual